1. Field of the Invention
The present invention generally relates to a method of forming a semiconductor device.
2. Description of the Related Art
In the transistors with a planar structure the substrate surface is used as a channel in the related art. It has become difficult to suppress a short channel effect due to miniaturization of semiconductor devices, and desired transistor characteristics cannot be obtained.
Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2006-339476 and JP-A-2007-081095 disclose using groove gate transistors to suppress the short channel effect.
In the groove gate transistors described in Japanese Unexamined Patent Application, First Publication, No. JP-A-2006-339476 and JP-A-2007-081095, surfaces of grooves formed in a semiconductor substrate are used as channels. Accordingly, an amount of reduction in the planar dimension can be compensated for with expansion in the depth direction of the groove, and it is possible to suppress the short channel effect.